Electrostatic discharge (ESD) has become increasingly problematic in semiconductor circuitry as circuit densities have grown and device sizes have become smaller. Very thin oxide layers are vulnerable to the voltages present in ESD events, which frequently occur in electronic devices that come into contact with a user's body. When a user picks up an electronic device, static charge stored between a user's body and ground can be coupled into the electronic device's electronic circuitry. As a result, ESD protection circuits are often required.
Older ESD protection circuits using snapback N-type metal oxide semiconductor (NMOS) technology and silicon controlled rectifier (SCR) technology have largely been replaced with ESD rail clamping circuits, particularly in integrated circuits with line widths less than 0.5 micrometers. Most of the pads on an integrated circuit are coupled to the power supply rails with reversed biased diodes; therefore, a positive ESD voltage spike will forward bias the diode connected to the direct current (DC) supply rail, thereby raising the voltage on the DC supply. An ESD clamping circuit is connected between the DC supply and ground and is triggered by the fast rising edge of the ESD spike. When a fast rising edge spike is shunted to the DC supply, the ESD clamping circuit turns on and applies a low impedance load between the DC supply and ground to dissipate the energy in the ESD voltage spike.
Two types of ESD clamping circuits are commonly used. The first type is a time-based ESD clamping circuit, wherein a low impedance load is applied upon an ESD event for a specified time period, such as two or three microseconds. Since the time constant is relatively long, this type of clamping circuit may turn on each time the power is applied to the integrated circuit. When the low impedance is applied, current surge results, which can be as high as several hundred milliamperes for the specified time period. For many applications, this may not be a problem. However, for circuits such as large switching arrays in some DC-to-DC converters, this can be unacceptable. In these designs, current surges may occur on the DC supply every time the circuit switches. This type of clamping circuit may falsely detect these surges on the power rails from DC-to-DC converter circuits as ESD events. Since the switching cycle is typically shorter than the microsecond clamping event, a large leakage current from the clamping device occurs. These factors can significantly increase average power consumption, which may be problematic, particularly in battery powered applications.
The second type of ESD clamping circuit is a latching ESD clamping circuit, wherein a low impedance load is applied upon an ESD event until the energy associated with the ESD event has been dissipated. The latching ESD clamping circuit latches into an “on” state, and remains in the “on” state until the DC supply voltage drops below a defined threshold. This type of clamping circuit does not turn on when power is applied to the integrated circuit, and is less susceptible to DC-to-DC converter power surges than the time-based ESD clamping circuit. Since the latching ESD clamping circuit is only on for the duration of an ESD event, current surges are smaller than the time-based ESD clamping circuit, resulting in less average current consumption and power dissipation than the time-based ESD clamping circuit.
Even though the latching ESD clamping circuit has several advantages over the time-based ESD clamping circuit, one disadvantage is that if the latching ESD clamping circuit becomes inadvertently latched due to a very fast current surge or other anomaly when the DC bias is high, there is a risk of it not releasing, or disrupting normal circuit operation. While the risk of inadvertent latching can be reduced through careful design, it may not be possible to eliminate it entirely. Therefore, a need exists for a latching ESD clamping circuit that releases quickly and reliably.